The present invention relates to a semiconductor component having a semiconductor substrate on which an insulating layer is formed, the insulating layer having a monolithically integrated capacitance structure formed in it.
Most analog circuit parts of hybrid digital/analog circuits require capacitors having a high capacitance value, a high level of linearity and high quality. In order to keep the costs for fabricating the component as low as possible, it is necessary for the fabrication of the capacitance structures to require as few process steps as possible. In addition, the progressive miniaturization of the components and integrated circuits also entails the demand for as little area requirement as possible for the capacitance structure.
U.S. Pat. No. 5,583,359 has disclosed a capacitance structure for an integrated circuit. In this case, a plurality of metal plates which form the electrodes of a stack capacitor are arranged above one another, isolated by dielectric layers. Each plane of a metal plate contains a metal line which is insulated from the respective plate. Contact with the metal lines is respectively made from both sides using via connections, as a result of which firstly all plates in odd-numbered positions and secondly all plates in even-numbered positions in the stack are electrically connected to one another. As a result of the plates in even-numbered positions being connected to a first connecting line and the plates in odd-numbered positions being connected to a second connecting line, adjacent plates are at different potentials and form respective pairs of electrodes in a plate capacitor. The capacitance surface is thus formed by the plate surfaces. One alternative embodiment of the electrodes is provided by virtue of the plates being in the form of strip-like lines which are arranged parallel to one another in a horizontal plane. All strips in uneven-numbered positions and all strips in even-numbered positions have one end connected to an electrical line, which is likewise in strip form, resulting in the formation of two lamellar structures which are arranged so as to interlock in the horizontal plane. This structure may also be produced in a plurality of planes arranged vertically with respect to one another. Drawbacks of this capacitance structure are the relatively low capacitance values per unit area and relatively high series resistances and series inductances of the structure.
A similar embodiment of a capacitance structure is known from U.S. Pat. No. 5,208,725. A plurality of first lines in strip form are arranged parallel to one another on a semiconductor substrate. A plurality of second lines are arranged congruently on these first lines, isolated by a dielectric layer. As a result of vertically and laterally adjacent lines being at different potentials, both capacitances between lines situated above one another and capacitances between adjacent lines are produced in one plane. In this structure too, the strip-like arrangement achieves only relatively low capacitance values per unit area and produces relatively high series resistances and series inductances.
A further capacitance structure is known from Aparicio, R. and Hajimiri, A.: Capacity Limits and Matching Properties of Lateral Flux Integrated Capacitors; IEEE Custom Integrated Circuits Conference, San Diego, May 6–9, 2001. Vertically arranged bar structures are arranged symmetrically with respect to one another. Each of the bars is constructed from metal regions and via regions which are arranged alternately on one another. The spots of metal on a bar are at a common potential. Spots of metal on adjacent bars are at different potentials. The via regions respectively make contact with two adjacent metal regions of a bar. A drawback of this structure is the only relatively low capacitance values per unit area.
A further drawback of the known capacitance structures is that they make only very inefficient use of the surface area which they take up on the chip and, measured against the required surface area, provide a relatively low capacitance value for the useful capacitance and hence have a relatively large parasitic capacitance component